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The Export Control (Amendment) (No. 2) Regulations 2025

Type Statutory-Instrument

Publication 2025-11-13

State In force

Department King's Printer of Acts of Parliament

Source legislation.gov.uk

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Made: 13th November 2025

Laid before Parliament: 17th November 2025

Coming into force: 16th December 2025

The Secretary of State makes these Regulations in exercise of the powers conferred by sections 1(1) and (3), 2(1) and (3), 4(1) and (3), 5(2), (4), (5) and (7) of the Export Control Act 2002[^f00001], Article 15(1) of Council Regulation (EC) No 428/2009 of 5 May 2009 setting up a Community regime for the control of exports, transfer, brokering and transit of dual-use items (Recast)[^f00002] and Article 24(1)(a) and (b) and (3)(b)(i) of Regulation (EU) 2019/125 of the European Parliament and of the Council of 16 January 2019 concerning trade in certain goods which could be used for capital punishment, torture or other cruel, inhuman or degrading treatment or punishment (codification)[^f00003].

Part 1 — PRELIMINARY

Citation, commencement and extent

1

(1) These Regulations may be cited as the Export Control (Amendment) (No. 2) Regulations 2025.

(2) These Regulations come into force on 16th December 2025.

(3) Parts 1 and 2 extend to England and Wales, Scotland and Northern Ireland.

(4) Parts 3 and 4 extend to England and Wales, and Scotland.

Part 2 — AMENDMENTS TO THE EXPORT CONTROL ORDER 2008

Amendments to the Export Control Order 2008

2

The Export Control Order 2008[^f00004] is amended in accordance with regulations 3 to 5.

Amendments to Schedule 2 (Military Goods, Software and Technology)

3

(1) Schedule 2 (Military Goods, Software and Technology) is amended as follows.

(2) After the definition of “Spacecraft”, insert—

“sub-orbital craft” means a craft having an enclosure designed for the transport of people or cargo which is designed to: operate above the stratosphere; perform a non-orbital trajectory; and land back on Earth with the people or cargo intact;

(3) In entry ML7.h., for the Technical Notes substitute—

Technical Notes: For the purposes of ML7.h.:	Technical Notes: For the purposes of ML7.h.:	Technical Notes: For the purposes of ML7.h.:
1.	‘Biopolymers’ are biological macromolecules as follows:	‘Biopolymers’ are biological macromolecules as follows:
	a.	Enzymes for specific chemical or biochemical reactions;
	b.	‘Anti-idiotypic’, ‘monoclonal’ or ‘polyclonal’ ‘antibodies’;
	c.	Specially designed or specially processed ‘receptors’.
2.	‘Anti-idiotypic antibodies’ means antibodies which bind to the specific antigen binding sites of other antibodies.	‘Anti-idiotypic antibodies’ means antibodies which bind to the specific antigen binding sites of other antibodies.
3.	‘Monoclonal antibodies’ means proteins which bind to one antigenic site and are produced by a single clone of cells.	‘Monoclonal antibodies’ means proteins which bind to one antigenic site and are produced by a single clone of cells.
4.	‘Polyclonal antibodies’ means a mixture of proteins which bind to the specific antigen and are produced by more than one clone of cells.	‘Polyclonal antibodies’ means a mixture of proteins which bind to the specific antigen and are produced by more than one clone of cells.
5.	‘Receptors’ means biological macromolecular structures capable of binding ligands, the binding of which affects physiological functions.	‘Receptors’ means biological macromolecular structures capable of binding ligands, the binding of which affects physiological functions.

(4) At the end of entry ML10.i., for “.” substitute “;”.

Amendments to Schedule 3 (UK Controlled Dual-Use Goods, Software and Technology)

4

(1) Schedule 3 (UK controlled dual-use goods, software and technology) is amended as follows.

(2) Omit the following definitions—

(a) “circuit element”;

(b) “digital computer”, including the Note to that definition;

(d) “electronic assemblies”;

(e) “Process Design Kit”.

(3) Omit the entries PL9013 to PL9015, including the headings, Notes and Technical Notes to those entries.

Amendments to Schedule 4 (Countries and Destinations Subject to Stricter Export or Trade Controls)

5

(1) Schedule 4 (Countries and Destinations Subject to Stricter Export or Trade Controls) is amended as follows.

(2) In Part 2 (embargoed and subject to transit control for military goods), omit—

(a) “Armenia”;

(b) “Azerbaijan”.

(3) In Part 4 (subject to transit control for category B goods), at the appropriate place, insert—

(a) “Armenia”;

(b) “Azerbaijan”.

Part 3 — AMENDMENTS TO COUNCIL REGULATION (EC) NO 428/2009

Amendments to Council Regulation (EC) No 428/2009

6

Annex I (list of dual-use items) to Council Regulation (EC) No 428/2009 of 5 May 2009 setting up a Community Regime for the control of exports, transfer, brokering and transit of dual-use items (Recast)[^f00005] is amended in accordance with regulations 7 to 13.

7

(1) The section headed Category 1 - Special Materials and Related Equipment is amended as follows.

(2) In the section headed 1B Test, Inspection and Production Equipment, in paragraph 2 of the Technical Notes to entry 1B228, for “contractor” substitute “contactor”.

(3) In the section headed 1C Materials, after entry 1C450, insert—

1C513	'High-entropy alloy' or 'refractory metal and alloy' powders, not specified in 1C002, having a surface modified with 'inoculants'.
Technical Notes: For the purposes of 1C513:	Technical Notes: For the purposes of 1C513:
1.	'High-entropy alloys' are alloys having at least 5 principal metallic elements, each having concentration within the range of 5 to 35 atomic percent, from the following list: Al, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zr, Nb, Mo, Hf, Ta or W.
2.	'Inoculants' are additives that promote grain nucleation and increase the total area of grain boundaries to inhibit solidification defects.
3.	‘Refractory metals and alloys' are metals and alloys of niobium, molybdenum, tungsten and tantalum.

Amendments to Category 2 - Materials Processing

8

(1) The section headed Category 2 - Materials Processing is amended as follows.

(2) In the section headed 2B Test, Inspection and Production Equipment, after entry 2B352, insert—

2B510	Additive manufacturing equipment, designed to produce metal or metal alloy components, having all of the following, and specially designed components therefor:	Additive manufacturing equipment, designed to produce metal or metal alloy components, having all of the following, and specially designed components therefor:	Additive manufacturing equipment, designed to produce metal or metal alloy components, having all of the following, and specially designed components therefor:
	a.	Having at least one of the following consolidation sources:	Having at least one of the following consolidation sources:
		1.	“ Lasers”;
		2.	Electron beam; or
		3.	Electric arc;
	b.	Having a controlled process atmosphere of any of the following:	Having a controlled process atmosphere of any of the following:
		1.	Inert gas; or
		2.	Vacuum (equal to or less than 100 Pa);
	c.	Having any of the following 'in-process monitoring' equipment in a 'coaxial configuration' or 'paraxial configuration':	Having any of the following 'in-process monitoring' equipment in a 'coaxial configuration' or 'paraxial configuration':
		1.	Imaging camera with a peak response in the wavelength range exceeding 380 nm but not exceeding 14 000 nm;
		2.	Pyrometer designed to measure temperatures greater than 1 273,15 K (1 000°C); or
		3.	Radiometer or spectrometer with a peak response in the wavelength range exceeding 380 nm but not exceeding 3 000 nm; and
	d.	A closed loop control system designed to modify the consolidation source parameters, build path, or equipment settings during the build cycle in response to feedback from 'in-process monitoring' equipment specified in 2B510.c.	A closed loop control system designed to modify the consolidation source parameters, build path, or equipment settings during the build cycle in response to feedback from 'in-process monitoring' equipment specified in 2B510.c.
Technical Notes: For the purposes of 2B510:	Technical Notes: For the purposes of 2B510:	Technical Notes: For the purposes of 2B510:	Technical Notes: For the purposes of 2B510:
1.	'In-process monitoring', also known as in-situ process monitoring, pertains to the observation and measurement of the additive manufacturing process including electromagnetic or thermal emissions from the melt pool.	'In-process monitoring', also known as in-situ process monitoring, pertains to the observation and measurement of the additive manufacturing process including electromagnetic or thermal emissions from the melt pool.	'In-process monitoring', also known as in-situ process monitoring, pertains to the observation and measurement of the additive manufacturing process including electromagnetic or thermal emissions from the melt pool.
2.	'Co-axial configuration', also known as on-axis or inline configuration, pertains to one or more sensors that are mounted in an optical path shared by the “laser” consolidation source.	'Co-axial configuration', also known as on-axis or inline configuration, pertains to one or more sensors that are mounted in an optical path shared by the “laser” consolidation source.	'Co-axial configuration', also known as on-axis or inline configuration, pertains to one or more sensors that are mounted in an optical path shared by the “laser” consolidation source.
3.	'Paraxial configuration' pertains to one or more sensors that are physically mounted onto or integrated into the “laser”, electron beam or electric arc consolidation source component.	'Paraxial configuration' pertains to one or more sensors that are physically mounted onto or integrated into the “laser”, electron beam or electric arc consolidation source component.	'Paraxial configuration' pertains to one or more sensors that are physically mounted onto or integrated into the “laser”, electron beam or electric arc consolidation source component.
4.	For both 'co-axial configuration' and 'paraxial configuration', the field of view of the sensor(s) is fixed to the moving reference frame of the consolidation source and moves in the same scan trajectories of the consolidation source throughout the build process.	For both 'co-axial configuration' and 'paraxial configuration', the field of view of the sensor(s) is fixed to the moving reference frame of the consolidation source and moves in the same scan trajectories of the consolidation source throughout the build process.	For both 'co-axial configuration' and 'paraxial configuration', the field of view of the sensor(s) is fixed to the moving reference frame of the consolidation source and moves in the same scan trajectories of the consolidation source throughout the build process.

(3) In the section headed 2D Software, in entry 2D001.a., for “2A001 or 2B001 to 2B009” substitute “2A001, 2B001 to 2B009 or 2B510”.

(4) In the section headed 2E Technology, after the Technical Note to the table (Deposition techniques) that appears after entry 2E301, insert—

“Technology”, as follows:	“Technology”, as follows:	“Technology”, as follows:
g.	“Technology”, not specified elsewhere, for the “development” or “production” of ‘coating systems’ having all of the following:	“Technology”, not specified elsewhere, for the “development” or “production” of ‘coating systems’ having all of the following:
	1.	Designed to protect ceramic “matrix” “composite” materials specified in 1C007 from corrosion; and
	2.	Designed to operate at temperatures exceeding 1 373,15 K (1 100°C).
Technical Note: For the purposes of 2E503.g.,‘coating systems’ consist of one or more layers (e.g., bond, interlayer, top coat) of material deposited on the substrate.	Technical Note: For the purposes of 2E503.g.,‘coating systems’ consist of one or more layers (e.g., bond, interlayer, top coat) of material deposited on the substrate.	Technical Note: For the purposes of 2E503.g.,‘coating systems’ consist of one or more layers (e.g., bond, interlayer, top coat) of material deposited on the substrate.

Amendments to Category 3 - Electronics

9

(1) The section headed Category 3 - Electronics is amended as follows.

(2) In the section headed 3A Systems, Equipment and Components—

(a) in Note 1, for “or 3A001.b.12.,” substitute “3A001.b.12. or 3A501.a.15.”;

(b) after the Technical Note to 3A001.a.2., insert—

N.B.: For cryogenic CMOS integrated circuits not specified in 3A001.a.2., see 3A501.a.15.

N.B.1.: For integrated circuits having field programmable logic devices that are combined with an analogue-to-digital converter, see 3A001.a.14. N.B.2.: For “electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs), see 3A502.i.

(d) after entry 3A001.a.9., insert—

N.B.: For integrated circuits, having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more, see 3A501.a.16.

(e) after entry 3A234, insert—

3A501	Electronic items, as follows:	Electronic items, as follows:	Electronic items, as follows:	Electronic items, as follows:	Electronic items, as follows:
	a.	General purpose integrated circuits, as follows:	General purpose integrated circuits, as follows:	General purpose integrated circuits, as follows:	General purpose integrated circuits, as follows:
		15.	Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, not specified in 3A001.a.2., designed to operate at an ambient temperature equal to or less (better) than 4,5 K (-268,65°C).	Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, not specified in 3A001.a.2., designed to operate at an ambient temperature equal to or less (better) than 4,5 K (-268,65°C).	Complementary Metal Oxide Semiconductor (CMOS) integrated circuits, not specified in 3A001.a.2., designed to operate at an ambient temperature equal to or less (better) than 4,5 K (-268,65°C).
			Technical Note: For the purposes of 3A501.a.15., CMOS integrated circuits are also referred to as cryogenic CMOS or cryoCMOS integrated circuits.	Technical Note: For the purposes of 3A501.a.15., CMOS integrated circuits are also referred to as cryogenic CMOS or cryoCMOS integrated circuits.	Technical Note: For the purposes of 3A501.a.15., CMOS integrated circuits are also referred to as cryogenic CMOS or cryoCMOS integrated circuits.
		16.	Integrated circuits having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more.	Integrated circuits having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more.	Integrated circuits having one or more digital processing units having a 'Total Processing Performance' ('TPP') of 6 000 or more.
			N.B.: For “digital computers” and “electronic assemblies” containing integrated circuits specified in 3A501.a.16., see 4A507.	N.B.: For “digital computers” and “electronic assemblies” containing integrated circuits specified in 3A501.a.16., see 4A507.	N.B.: For “digital computers” and “electronic assemblies” containing integrated circuits specified in 3A501.a.16., see 4A507.
			Technical Notes: For the purposes of 3A501.a.16.:	Technical Notes: For the purposes of 3A501.a.16.:	Technical Notes: For the purposes of 3A501.a.16.:
			1.	'Total processing performance' ('TPP') is 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit.	'Total processing performance' ('TPP') is 2 x 'MacTOPS' x 'bit length of the operation', aggregated over all processing units on the integrated circuit.
				a.	'MacTOPS' is the theoretical peak number of tera (10¹²) operations per second for multiply-accumulate computation, D=AxB+C).
				b.	The 2 in the 'TPP' formula is based on the industry convention of counting one multiply-accumulate computation, D=AxB+C, as 2 operations for the purpose of datasheets. Therefore, 2 x MacTOPS may correspond to the reported TOPS or FLOPS on a datasheet.
				c.	'Bit length of the operation' for a multiply-accumulate computation is the largest bit-length of the inputs to the multiply operation.
				d.	Aggregate the TPPs for each processing unit on the integrated circuit to arrive at a total. 'TPP' = TPP1 + TPP2 +… + TPPn (where n is the number of processing units on the integrated circuit).
			2.	The rate of 'MacTOPS' is to be calculated at its maximum value theoretically possible. The rate of 'MacTOPS' is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the 'TPP' threshold of 6 000 can be met with 750 tera integer operations (or 2 x 375 'MacTOPS') at 8 bits or 300 tera FLOPS (or 2 x 150 'MacTOPS') at 16 bits. If the IC is designed for MAC computation with multiple bit lengths that achieve different 'TPP' values, the highest 'TPP' value should be evaluated against parameters in 3A501.a.16.	The rate of 'MacTOPS' is to be calculated at its maximum value theoretically possible. The rate of 'MacTOPS' is assumed to be the highest value the manufacturer claims in a manual or brochure for the integrated circuit. For example, the 'TPP' threshold of 6 000 can be met with 750 tera integer operations (or 2 x 375 'MacTOPS') at 8 bits or 300 tera FLOPS (or 2 x 150 'MacTOPS') at 16 bits. If the IC is designed for MAC computation with multiple bit lengths that achieve different 'TPP' values, the highest 'TPP' value should be evaluated against parameters in 3A501.a.16.
			3.	For integrated circuits, specified in 3A501.a.16., that provide processing of both sparse and dense matrices, the 'TPP' values are the values for processing of dense matrices (e.g., without sparsity).	For integrated circuits, specified in 3A501.a.16., that provide processing of both sparse and dense matrices, the 'TPP' values are the values for processing of dense matrices (e.g., without sparsity).
	b.	Microwave or millimetre wave items as follows:	Microwave or millimetre wave items as follows:	Microwave or millimetre wave items as follows:	Microwave or millimetre wave items as follows:
		13.	Parametric signal amplifiers having all of the following:	Parametric signal amplifiers having all of the following:	Parametric signal amplifiers having all of the following:
			a.	Designed for operation at an ambient temperature below 1 K (-272,15ºC);	Designed for operation at an ambient temperature below 1 K (-272,15ºC);
			b.	Designed for operation at any frequency from 2 GHz up to and including 15 GHz; and	Designed for operation at any frequency from 2 GHz up to and including 15 GHz; and
			c.	A noise figure less (better) than 0,015 dB at any frequency from 2 GHz up to and including 15 GHz at 1 K (-272,15ºC);	A noise figure less (better) than 0,015 dB at any frequency from 2 GHz up to and including 15 GHz at 1 K (-272,15ºC);
			Note: Parametric signal amplifiers include Travelling Wave Parametric Amplifiers (TWPAs).	Note: Parametric signal amplifiers include Travelling Wave Parametric Amplifiers (TWPAs).	Note: Parametric signal amplifiers include Travelling Wave Parametric Amplifiers (TWPAs).
			Technical Note: For the purposes of 3A501.b.13., parametric signal amplifiers may also be referred to as Quantum-Limited Amplifiers (QLAs).	Technical Note: For the purposes of 3A501.b.13., parametric signal amplifiers may also be referred to as Quantum-Limited Amplifiers (QLAs).	Technical Note: For the purposes of 3A501.b.13., parametric signal amplifiers may also be referred to as Quantum-Limited Amplifiers (QLAs).
3A502	General purpose “electronic assemblies”, modules and equipment, as follows:	General purpose “electronic assemblies”, modules and equipment, as follows:	General purpose “electronic assemblies”, modules and equipment, as follows:	General purpose “electronic assemblies”, modules and equipment, as follows:	General purpose “electronic assemblies”, modules and equipment, as follows:
	i.	“Electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs) and having an ‘aggregate lookup table input count' of greater than or equal to 1 800 000.	“Electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs) and having an ‘aggregate lookup table input count' of greater than or equal to 1 800 000.	“Electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs) and having an ‘aggregate lookup table input count' of greater than or equal to 1 800 000.	“Electronic assemblies”, modules or equipment, containing one or more 'user configurable' Field Programmable Logic Devices (FPLDs) and having an ‘aggregate lookup table input count' of greater than or equal to 1 800 000.
		N.B.: For items having FPLDs that are combined with an Analogue-to-Digital Converter (ADC), rated for extended operating temperatures or are radiation hardened, or have cryptographic functionality, see 3A002.h., 4A001.a., and 5A002.a. respectively.	N.B.: For items having FPLDs that are combined with an Analogue-to-Digital Converter (ADC), rated for extended operating temperatures or are radiation hardened, or have cryptographic functionality, see 3A002.h., 4A001.a., and 5A002.a. respectively.	N.B.: For items having FPLDs that are combined with an Analogue-to-Digital Converter (ADC), rated for extended operating temperatures or are radiation hardened, or have cryptographic functionality, see 3A002.h., 4A001.a., and 5A002.a. respectively.	N.B.: For items having FPLDs that are combined with an Analogue-to-Digital Converter (ADC), rated for extended operating temperatures or are radiation hardened, or have cryptographic functionality, see 3A002.h., 4A001.a., and 5A002.a. respectively.
		Technical Notes: For the purposes of 3A502.i.:	Technical Notes: For the purposes of 3A502.i.:	Technical Notes: For the purposes of 3A502.i.:	Technical Notes: For the purposes of 3A502.i.:
		1.	'User configurable' means a user can configure or modify the logic cells or interconnects between logic cells within the FPLD logic fabric to prescribe the specific function that the 3A502.i. item performs.	'User configurable' means a user can configure or modify the logic cells or interconnects between logic cells within the FPLD logic fabric to prescribe the specific function that the 3A502.i. item performs.	'User configurable' means a user can configure or modify the logic cells or interconnects between logic cells within the FPLD logic fabric to prescribe the specific function that the 3A502.i. item performs.
		2.	'Aggregate lookup table input count' is the sum of the number of independent inputs available to each programmable Lookup Table (LUT), as accumulated across all physical LUTs contained within a FPLD or other programmable item. An example is: a circuit board containing 2 FPGAs, each having 150 000 programmable LUTs with 6 inputs, would have an 'aggregate lookup table input count' of 2 x 150 000 x 6 = 1 800 000.	'Aggregate lookup table input count' is the sum of the number of independent inputs available to each programmable Lookup Table (LUT), as accumulated across all physical LUTs contained within a FPLD or other programmable item. An example is: a circuit board containing 2 FPGAs, each having 150 000 programmable LUTs with 6 inputs, would have an 'aggregate lookup table input count' of 2 x 150 000 x 6 = 1 800 000.	'Aggregate lookup table input count' is the sum of the number of independent inputs available to each programmable Lookup Table (LUT), as accumulated across all physical LUTs contained within a FPLD or other programmable item. An example is: a circuit board containing 2 FPGAs, each having 150 000 programmable LUTs with 6 inputs, would have an 'aggregate lookup table input count' of 2 x 150 000 x 6 = 1 800 000.
3A504	Cryogenic cooling systems and components, as follows:	Cryogenic cooling systems and components, as follows:	Cryogenic cooling systems and components, as follows:	Cryogenic cooling systems and components, as follows:	Cryogenic cooling systems and components, as follows:
	a.	Systems rated to provide a cooling power greater than or equal to 600 μW at or below a temperature of 0,1 K (-273,05°C) for a period of greater than 48 hours;	Systems rated to provide a cooling power greater than or equal to 600 μW at or below a temperature of 0,1 K (-273,05°C) for a period of greater than 48 hours;	Systems rated to provide a cooling power greater than or equal to 600 μW at or below a temperature of 0,1 K (-273,05°C) for a period of greater than 48 hours;	Systems rated to provide a cooling power greater than or equal to 600 μW at or below a temperature of 0,1 K (-273,05°C) for a period of greater than 48 hours;
	b.	Two-stage pulse tube cryocoolers rated to maintain a temperature below 4 K (-269,15°C) and provide a cooling power greater than or equal to 1,5 W at or below a temperature of 4,2 K (-268,95°C).	Two-stage pulse tube cryocoolers rated to maintain a temperature below 4 K (-269,15°C) and provide a cooling power greater than or equal to 1,5 W at or below a temperature of 4,2 K (-268,95°C).	Two-stage pulse tube cryocoolers rated to maintain a temperature below 4 K (-269,15°C) and provide a cooling power greater than or equal to 1,5 W at or below a temperature of 4,2 K (-268,95°C).	Two-stage pulse tube cryocoolers rated to maintain a temperature below 4 K (-269,15°C) and provide a cooling power greater than or equal to 1,5 W at or below a temperature of 4,2 K (-268,95°C).

(3) In the section headed 3B Test, Inspection and Production Equipment—

(a) after entry 3B001.a., insert—

N.B.: For equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), see 3B501.a.4.

(b) after entry 3B001.f.1., insert—

N.B.: SEE ALSO 3B501.f.

N.B.: SEE ALSO 3B501.l.

(d) after entry 3B002, insert—

3B501	Equipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:	Equipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:	Equipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:	Equipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:	Equipment for the manufacturing of semiconductor devices or materials, as follows and specially designed components and accessories therefor:
	a.	Equipment designed for epitaxial growth as follows:	Equipment designed for epitaxial growth as follows:	Equipment designed for epitaxial growth as follows:	Equipment designed for epitaxial growth as follows:
		1.	Not used;	Not used;	Not used;
		2.	Not used;	Not used;	Not used;
		3.	Not used;	Not used;	Not used;
		4.	Equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), and having all of the following:	Equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), and having all of the following:	Equipment designed for epitaxial growth of silicon (Si) or silicon germanium (SiGe), and having all of the following:
			a.	At least one preclean chamber designed to provide a surface preparation means to clean the surface of the wafer; and	At least one preclean chamber designed to provide a surface preparation means to clean the surface of the wafer; and
			b.	An epitaxial deposition chamber designed to operate at a temperature below 958 K (685°C);	An epitaxial deposition chamber designed to operate at a temperature below 958 K (685°C);
		Note: 3B501.a.4. includes Atomic Layer Epitaxy (ALE) equipment.	Note: 3B501.a.4. includes Atomic Layer Epitaxy (ALE) equipment.	Note: 3B501.a.4. includes Atomic Layer Epitaxy (ALE) equipment.	Note: 3B501.a.4. includes Atomic Layer Epitaxy (ALE) equipment.
	b.	Not used;	Not used;	Not used;	Not used;
	c.	Not used;	Not used;	Not used;	Not used;
	d.	Not used;	Not used;	Not used;	Not used;
	e.	Not used;	Not used;	Not used;	Not used;
	f.	Lithography equipment as follows:	Lithography equipment as follows:	Lithography equipment as follows:	Lithography equipment as follows:
		1.	Align and expose step and repeat (direct step on wafer) or step and scan (scanner) lithography equipment for wafer processing, not specified in 3B001.f., using photo-optical or X-ray methods, and having any of the following:	Align and expose step and repeat (direct step on wafer) or step and scan (scanner) lithography equipment for wafer processing, not specified in 3B001.f., using photo-optical or X-ray methods, and having any of the following:	Align and expose step and repeat (direct step on wafer) or step and scan (scanner) lithography equipment for wafer processing, not specified in 3B001.f., using photo-optical or X-ray methods, and having any of the following:
			a.	A light source wavelength shorter than 193 nm; or	A light source wavelength shorter than 193 nm; or
			b.	Having all of the following:	Having all of the following:
				1.	A light source wavelength equal to or longer than 193 nm;
				2.	Capable of producing a pattern with a 'Minimum Resolvable Feature size' ('MRF') of 45 nm or less; and
				3.	A maximum 'dedicated chuck overlay' value of less than or equal to 1,5 nm;
		Technical Notes: For the purposes of 3B501.f.1.b.:	Technical Notes: For the purposes of 3B501.f.1.b.:	Technical Notes: For the purposes of 3B501.f.1.b.:	Technical Notes: For the purposes of 3B501.f.1.b.:
		1.	The 'Minimum Resolvable Feature size' ('MRF') is calculated by the following formula: $' M R F ' = ( a n e x p o s u r e l i g h t s o u r c e w a v e l e n g t h i n n m ) × ( K f a c t o r ) m a x i m u m n u m e r i c a l a p e r t u r e$	The 'Minimum Resolvable Feature size' ('MRF') is calculated by the following formula: $' M R F ' = ( a n e x p o s u r e l i g h t s o u r c e w a v e l e n g t h i n n m ) × ( K f a c t o r ) m a x i m u m n u m e r i c a l a p e r t u r e$	The 'Minimum Resolvable Feature size' ('MRF') is calculated by the following formula: $' M R F ' = ( a n e x p o s u r e l i g h t s o u r c e w a v e l e n g t h i n n m ) × ( K f a c t o r ) m a x i m u m n u m e r i c a l a p e r t u r e$
			where the K factor = 0,25 'MRF' is also known as resolution.	where the K factor = 0,25 'MRF' is also known as resolution.	where the K factor = 0,25 'MRF' is also known as resolution.
		2.	'Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system. 'Dedicated chuck overlay' is also known as single machine overlay.	'Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system. 'Dedicated chuck overlay' is also known as single machine overlay.	'Dedicated chuck overlay' is the alignment accuracy of a new pattern to an existing pattern printed on a wafer by the same lithographic system. 'Dedicated chuck overlay' is also known as single machine overlay.
		N.B.: SEE ALSO 3B001.f.1.	N.B.: SEE ALSO 3B001.f.1.	N.B.: SEE ALSO 3B001.f.1.	N.B.: SEE ALSO 3B001.f.1.
	g.	Not used;	Not used;	Not used;	Not used;
	h.	Not used;	Not used;	Not used;	Not used;
	i.	Not used;	Not used;	Not used;	Not used;
	j.	Not used;	Not used;	Not used;	Not used;
	k.	Equipment designed for dry etching having any of the following:	Equipment designed for dry etching having any of the following:	Equipment designed for dry etching having any of the following:	Equipment designed for dry etching having any of the following:
		1.	Equipment designed or modified for isotropic dry etching, having a largest 'silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1; or	Equipment designed or modified for isotropic dry etching, having a largest 'silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1; or	Equipment designed or modified for isotropic dry etching, having a largest 'silicon germanium-to-silicon (SiGe:Si) etch selectivity' of greater than or equal to 100:1; or
		2.	Equipment designed or modified for anisotropic dry etching, having all of the following:	Equipment designed or modified for anisotropic dry etching, having all of the following:	Equipment designed or modified for anisotropic dry etching, having all of the following:
			a.	Radio Frequency (RF) power source(s) with at least one pulsed RF output;	Radio Frequency (RF) power source(s) with at least one pulsed RF output;
			b.	One or more fast gas switching valve(s) with switching time less than 300 ms; and	One or more fast gas switching valve(s) with switching time less than 300 ms; and
			c.	Electrostatic chuck with 20 or more individually controllable variable temperature elements;	Electrostatic chuck with 20 or more individually controllable variable temperature elements;
		Note 1.: 3B501.k. includes etching by 'radicals', ions, sequential reactions or non-sequential reactions.	Note 1.: 3B501.k. includes etching by 'radicals', ions, sequential reactions or non-sequential reactions.	Note 1.: 3B501.k. includes etching by 'radicals', ions, sequential reactions or non-sequential reactions.	Note 1.: 3B501.k. includes etching by 'radicals', ions, sequential reactions or non-sequential reactions.
		Note 2.: 3B501.k. includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching or plasma quasiatomic layer etching.	Note 2.: 3B501.k. includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching or plasma quasiatomic layer etching.	Note 2.: 3B501.k. includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching or plasma quasiatomic layer etching.	Note 2.: 3B501.k. includes etching using RF pulse excited plasma, pulsed duty cycle excited plasma, pulsed voltage on electrodes modified plasma, cyclic injection and purging of gases combined with a plasma, plasma atomic layer etching or plasma quasiatomic layer etching.
		Technical Notes: For the purposes of 3B501.k.:	Technical Notes: For the purposes of 3B501.k.:	Technical Notes: For the purposes of 3B501.k.:	Technical Notes: For the purposes of 3B501.k.:
		1.	'Silicon germanium-to-silicon (SiGe:Si) etch selectivity' is measured for a Ge concentration of greater than or equal to 30% (Si0,7 Ge0,3).	'Silicon germanium-to-silicon (SiGe:Si) etch selectivity' is measured for a Ge concentration of greater than or equal to 30% (Si0,7 Ge0,3).	'Silicon germanium-to-silicon (SiGe:Si) etch selectivity' is measured for a Ge concentration of greater than or equal to 30% (Si0,7 Ge0,3).
		2.	'Radical' is defined as an atom, molecule or ion that has an unpaired electron in an open electron shell configuration.	'Radical' is defined as an atom, molecule or ion that has an unpaired electron in an open electron shell configuration.	'Radical' is defined as an atom, molecule or ion that has an unpaired electron in an open electron shell configuration.
	l.	'Extreme Ultraviolet' ('EUV') masks and 'EUV' reticles, designed for integrated circuits, not specified in 3B001.g., and having a mask “substrate blank” specified in 3B001.j.;	'Extreme Ultraviolet' ('EUV') masks and 'EUV' reticles, designed for integrated circuits, not specified in 3B001.g., and having a mask “substrate blank” specified in 3B001.j.;	'Extreme Ultraviolet' ('EUV') masks and 'EUV' reticles, designed for integrated circuits, not specified in 3B001.g., and having a mask “substrate blank” specified in 3B001.j.;	'Extreme Ultraviolet' ('EUV') masks and 'EUV' reticles, designed for integrated circuits, not specified in 3B001.g., and having a mask “substrate blank” specified in 3B001.j.;
		Technical Notes:	Technical Notes:	Technical Notes:	Technical Notes:
		1.	For the purposes of 3B501.l., masks or reticles with a mounted pellicle are considered masks and reticles.	For the purposes of 3B501.l., masks or reticles with a mounted pellicle are considered masks and reticles.	For the purposes of 3B501.l., masks or reticles with a mounted pellicle are considered masks and reticles.
		2.	For the purposes of 3B501.l., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.	For the purposes of 3B501.l., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.	For the purposes of 3B501.l., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.
	m.	'Pellicles' specially designed for 'Extreme Ultraviolet' ('EUV') lithography;	'Pellicles' specially designed for 'Extreme Ultraviolet' ('EUV') lithography;	'Pellicles' specially designed for 'Extreme Ultraviolet' ('EUV') lithography;	'Pellicles' specially designed for 'Extreme Ultraviolet' ('EUV') lithography;
		Technical Notes:	Technical Notes:	Technical Notes:	Technical Notes:
		1.	For the purposes of 3B501.m., a 'pellicle' is a membrane integrated with a frame, designed to protect a mask or reticle from particle contamination.	For the purposes of 3B501.m., a 'pellicle' is a membrane integrated with a frame, designed to protect a mask or reticle from particle contamination.	For the purposes of 3B501.m., a 'pellicle' is a membrane integrated with a frame, designed to protect a mask or reticle from particle contamination.
		2.	For the purposes of 3B501.m., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.	For the purposes of 3B501.m., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.	For the purposes of 3B501.m., 'Extreme Ultraviolet' ('EUV') means electromagnetic spectrum wavelengths greater than 5 nm and less than 124 nm.
	n.	Semiconductor manufacturing deposition equipment as follows:	Semiconductor manufacturing deposition equipment as follows:	Semiconductor manufacturing deposition equipment as follows:	Semiconductor manufacturing deposition equipment as follows:
		1.	Atomic Layer Deposition (ALD) equipment as follows:	Atomic Layer Deposition (ALD) equipment as follows:	Atomic Layer Deposition (ALD) equipment as follows:
			a.	Equipment designed for the deposition of tungsten to fill an entire interconnect or in a channel less than 40 nm wide;	Equipment designed for the deposition of tungsten to fill an entire interconnect or in a channel less than 40 nm wide;
			b.	Equipment designed for 'area selective deposition' of a metal or metal nitride sidewall barrier using an organometallic compound precursor;	Equipment designed for 'area selective deposition' of a metal or metal nitride sidewall barrier using an organometallic compound precursor;
				Technical Note: For the purposes of 3B501.n.1.b., 'area selective deposition' refers to the deposition of material on the sidewall but not the bottom of a feature.	Technical Note: For the purposes of 3B501.n.1.b., 'area selective deposition' refers to the deposition of material on the sidewall but not the bottom of a feature.
			c.	Equipment designed for the deposition of a 'work function metal' composed of titanium aluminium carbide (TiAlC) and having a work function greater than 4 eV, and having all of the following:	Equipment designed for the deposition of a 'work function metal' composed of titanium aluminium carbide (TiAlC) and having a work function greater than 4 eV, and having all of the following:
				1.	More than one metal source of which one is functioning as an aluminium precursor source; and
				2.	A precursor vessel designed to operate at a temperature greater than or equal to 303,15 K (30℃);
				Technical Note: For the purposes of 3B501.n.1.c., 'work function metal' is a material that controls the threshold voltage of a transistor.	Technical Note: For the purposes of 3B501.n.1.c., 'work function metal' is a material that controls the threshold voltage of a transistor.
		2.	Equipment designed for cobalt electroplating or cobalt electroless-plating deposition processes;	Equipment designed for cobalt electroplating or cobalt electroless-plating deposition processes;	Equipment designed for cobalt electroplating or cobalt electroless-plating deposition processes;
		3.	Equipment designed for Chemical Vapour Deposition (CVD) of cobalt fill metal;	Equipment designed for Chemical Vapour Deposition (CVD) of cobalt fill metal;	Equipment designed for Chemical Vapour Deposition (CVD) of cobalt fill metal;
		4.	Equipment designed for 'selective bottom-up' Chemical Vapour Deposition (CVD) of tungsten fill metal;	Equipment designed for 'selective bottom-up' Chemical Vapour Deposition (CVD) of tungsten fill metal;	Equipment designed for 'selective bottom-up' Chemical Vapour Deposition (CVD) of tungsten fill metal;
			Technical Note: For the purposes of 3B501.n.4., ‘selective bottom-up’ refers to the preferential deposition of material on the bottom relative to the sidewall.	Technical Note: For the purposes of 3B501.n.4., ‘selective bottom-up’ refers to the preferential deposition of material on the bottom relative to the sidewall.	Technical Note: For the purposes of 3B501.n.4., ‘selective bottom-up’ refers to the preferential deposition of material on the bottom relative to the sidewall.
		5.	Equipment designed for void-free plasma enhanced deposition of a layer with a dielectric constant less than 3,3, in 'gaps' having an 'aspect ratio' equal to or greater than 1:1 and a width less than 25 nm;	Equipment designed for void-free plasma enhanced deposition of a layer with a dielectric constant less than 3,3, in 'gaps' having an 'aspect ratio' equal to or greater than 1:1 and a width less than 25 nm;	Equipment designed for void-free plasma enhanced deposition of a layer with a dielectric constant less than 3,3, in 'gaps' having an 'aspect ratio' equal to or greater than 1:1 and a width less than 25 nm;
			Technical Notes: For the purposes of 3B501.n.5.:	Technical Notes: For the purposes of 3B501.n.5.:	Technical Notes: For the purposes of 3B501.n.5.:
			1.	A 'gap' is the space between metal lines.	A 'gap' is the space between metal lines.
			2.	The 'aspect ratio' (depth : width) is defined as the ratio of the depth to the width of the gap between the metal lines.	The 'aspect ratio' (depth : width) is defined as the ratio of the depth to the width of the gap between the metal lines.
		6.	Equipment designed for the deposition of a ruthenium layer using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);	Equipment designed for the deposition of a ruthenium layer using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);	Equipment designed for the deposition of a ruthenium layer using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
		7.	Equipment designed for multistep processing in multiple chambers and maintaining high vacuum or inert environment during transfer between process steps, as follows:	Equipment designed for multistep processing in multiple chambers and maintaining high vacuum or inert environment during transfer between process steps, as follows:	Equipment designed for multistep processing in multiple chambers and maintaining high vacuum or inert environment during transfer between process steps, as follows:
			a.	Equipment designed to fabricate a metal contact by performing all of the following processes:	Equipment designed to fabricate a metal contact by performing all of the following processes:
				1.	Surface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia, while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);
				2.	Surface treatment plasma process using oxygen or ozone, while maintaining the wafer substrate at a temperature greater than 313,15 K (40°C) and less than 773,15 K (500°C); and
				3.	Deposition of a tungsten layer while maintaining the wafer substrate at a temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C);
			b.	Equipment designed to fabricate a metal contact by performing all of the following processes:	Equipment designed to fabricate a metal contact by performing all of the following processes:
				1.	Surface treatment plasma process using a remote plasma generator and an ion filter; and
				2.	Deposition of a cobalt layer selectively onto copper using an organometallic compound precursor;
			c.	Equipment designed to fabricate a metal contact by performing all of the following processes:	Equipment designed to fabricate a metal contact by performing all of the following processes:
				1.	Deposition of a titanium nitride or tungsten carbide layer, using an organometallic compound precursor, while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
				2.	Deposition of a cobalt layer using a physical sputter deposition technique and having a process pressure greater than 1,33x10 ⁻¹ Pa (1 mTorr) and less than 1,33x10 ¹ Pa (100 mTorr), while maintaining the wafer substrate at temperature less than 773,15 K (500°C); and
				3.	Deposition of a cobalt layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 ² Pa (1 Torr) and less than 1,33x10 ⁴ Pa (100 Torr), while maintaining the wafer substrate at temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C);
			d.	Equipment designed to fabricate copper interconnects by performing all of the following processes:	Equipment designed to fabricate copper interconnects by performing all of the following processes:
				1.	Deposition of a cobalt or ruthenium layer using an organometallic compound precursor and having a process pressure greater than 1,33x10 ² Pa (1 Torr) and less than 1,33x10 ⁴ Pa (100 Torr), while maintaining the wafer substrate at a temperature greater than 293,15 K (20°C) and less than 773,15 K (500°C); and
				2.	Deposition of a copper layer using a physical vapour deposition technique having a process pressure greater than 1,33x10 ⁻¹ Pa (1 mTorr) and less than 1,33x10 ¹ Pa (100 mTorr), while maintaining the wafer substrate at a temperature less than 773,15 K (500°C);
		8.	Equipment designed to fabricate a metal contact by multistep processing within a single chamber by performing all of the following:	Equipment designed to fabricate a metal contact by multistep processing within a single chamber by performing all of the following:	Equipment designed to fabricate a metal contact by multistep processing within a single chamber by performing all of the following:
			a.	Deposition of a tungsten layer, using an organometallic compound precursor, while maintaining the wafer substrate temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C); and	Deposition of a tungsten layer, using an organometallic compound precursor, while maintaining the wafer substrate temperature greater than 373,15 K (100°C) and less than 773,15 K (500°C); and
			b.	Surface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia (NH ₃).	Surface treatment plasma process using hydrogen, hydrogen and nitrogen, or ammonia (NH ₃).
3B503	Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:	Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:	Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:	Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:	Scanning Electron Microscope (SEM) equipment designed for imaging semiconductor devices or integrated circuits, having all of the following:
	a.	Stage placement accuracy less (better) than 30 nm;	Stage placement accuracy less (better) than 30 nm;	Stage placement accuracy less (better) than 30 nm;	Stage placement accuracy less (better) than 30 nm;
	b.	Stage positioning measurement performed using laser interferometry;	Stage positioning measurement performed using laser interferometry;	Stage positioning measurement performed using laser interferometry;	Stage positioning measurement performed using laser interferometry;
	c.	Position calibration within a Field-Of-View (FOV) based on laser interferometer length-scale measurement;	Position calibration within a Field-Of-View (FOV) based on laser interferometer length-scale measurement;	Position calibration within a Field-Of-View (FOV) based on laser interferometer length-scale measurement;	Position calibration within a Field-Of-View (FOV) based on laser interferometer length-scale measurement;
	d.	Collection and storage of images having more than 2 x 10 ⁸ pixels;	Collection and storage of images having more than 2 x 10 ⁸ pixels;	Collection and storage of images having more than 2 x 10 ⁸ pixels;	Collection and storage of images having more than 2 x 10 ⁸ pixels;
	e.	FOV overlap of less than 5% in vertical and horizontal directions;	FOV overlap of less than 5% in vertical and horizontal directions;	FOV overlap of less than 5% in vertical and horizontal directions;	FOV overlap of less than 5% in vertical and horizontal directions;
	f.	Stitching overlap of FOV less than 50 nm; and	Stitching overlap of FOV less than 50 nm; and	Stitching overlap of FOV less than 50 nm; and	Stitching overlap of FOV less than 50 nm; and
	g.	Accelerating voltage more than 21 kV;	Accelerating voltage more than 21 kV;	Accelerating voltage more than 21 kV;	Accelerating voltage more than 21 kV;
Note 1.: 3B503 includes SEM equipment designed for chip design recovery.	Note 1.: 3B503 includes SEM equipment designed for chip design recovery.	Note 1.: 3B503 includes SEM equipment designed for chip design recovery.	Note 1.: 3B503 includes SEM equipment designed for chip design recovery.	Note 1.: 3B503 includes SEM equipment designed for chip design recovery.	Note 1.: 3B503 includes SEM equipment designed for chip design recovery.
Note 2.: 3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).	Note 2.: 3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).	Note 2.: 3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).	Note 2.: 3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).	Note 2.: 3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).	Note 2.: 3B503 does not control SEM equipment designed to accept a Semiconductor Equipment and Materials International (SEMI) standard wafer carrier, such as a 200 mm or larger Front Opening Unified Pod (FOUP).
3B504	Cryogenic wafer probing equipment having all of the following:	Cryogenic wafer probing equipment having all of the following:	Cryogenic wafer probing equipment having all of the following:	Cryogenic wafer probing equipment having all of the following:	Cryogenic wafer probing equipment having all of the following:
	a.	Designed to test devices at temperatures less than or equal to 4,5 K (-268,65°C); and	Designed to test devices at temperatures less than or equal to 4,5 K (-268,65°C); and	Designed to test devices at temperatures less than or equal to 4,5 K (-268,65°C); and	Designed to test devices at temperatures less than or equal to 4,5 K (-268,65°C); and
	b.	Designed to accommodate wafer diameters greater than or equal to 100 mm.	Designed to accommodate wafer diameters greater than or equal to 100 mm.	Designed to accommodate wafer diameters greater than or equal to 100 mm.	Designed to accommodate wafer diameters greater than or equal to 100 mm.

(4) In the section headed 3C Materials—

(a) in entry 3C001, for “in PL9013.b. in Schedule 3 to the Export Control Order 2008,” substitute “in 3C507,”;

(b) in the N.B. to entry 3C005.b., for “‘substrate’” substitute ““substrate””;

3C507	Epitaxial materials consisting of a “substrate” having at least one epitaxially grown layer of any of the following:	Epitaxial materials consisting of a “substrate” having at least one epitaxially grown layer of any of the following:
	a.	Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
	b.	Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
3C508	Fluorides, hydrides, or chlorides of silicon or germanium, containing any of the following:	Fluorides, hydrides, or chlorides of silicon or germanium, containing any of the following:
	a.	Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
	b.	Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
3C509	Silicon, silicon oxides, germanium or germanium oxides, containing any of the following:	Silicon, silicon oxides, germanium or germanium oxides, containing any of the following:
	a.	Silicon having an isotopic impurity less than 0,08% of silicon isotopes other than silicon-28 or silicon-30; or
	b.	Germanium having an isotopic impurity less than 0,08% of germanium isotopes other than germanium-70, germanium-72, germanium-74, or germanium-76.
Note: 3C509 includes “substrates”, lumps, ingots, boules and preforms.	Note: 3C509 includes “substrates”, lumps, ingots, boules and preforms.	Note: 3C509 includes “substrates”, lumps, ingots, boules and preforms.

(5) In the section headed 3D Software—

(a) in entry 3D001, after “3A002.h.”, insert “, 3A501.b.13.”;

(b) in entry 3D002, for “3B001.a. to f., 3B002 or 3A225” substitute “3A225, 3B001.a. to 3B001.f., 3B002, 3B501.a.4., 3B501.f.1., 3B501.k. or 3B501.n.”;

3D507	“Software” designed to extract ‘GDSII’ or equivalent standard layout data and perform layer-to-layer alignment from Scanning Electron Microscope (SEM) images, and generate multi-layer ‘GDSII’ data or the circuit netlist.
Technical Note: For the purposes of 3D507, ‘GDSII’ (‘Graphic Design System II’) is a database file format for data exchange of integrated circuit artwork or integrated circuit layout artwork.	Technical Note: For the purposes of 3D507, ‘GDSII’ (‘Graphic Design System II’) is a database file format for data exchange of integrated circuit artwork or integrated circuit layout artwork.

(6) In the section headed 3E Technology, after entry 3E225, insert—

3E505	“ Technology” according to the General Technology Note for the “development”or “production” of integrated circuits or devices, using “Gate-All-Around Field-Effect Transistor” (“GAAFET”) structures.	“ Technology” according to the General Technology Note for the “development”or “production” of integrated circuits or devices, using “Gate-All-Around Field-Effect Transistor” (“GAAFET”) structures.
Note 1.: 3E505 includes ‘process recipes’.	Note 1.: 3E505 includes ‘process recipes’.	Note 1.: 3E505 includes ‘process recipes’.
Note 2.: 3E505 does not control tool qualification or maintenance.	Note 2.: 3E505 does not control tool qualification or maintenance.	Note 2.: 3E505 does not control tool qualification or maintenance.
Note 3.: 3E505 does not control ‘Process Design Kits’ (‘PDKs’) unless they include libraries implementing functions or technologies for items specified in 3A001 or 3A501.	Note 3.: 3E505 does not control ‘Process Design Kits’ (‘PDKs’) unless they include libraries implementing functions or technologies for items specified in 3A001 or 3A501.	Note 3.: 3E505 does not control ‘Process Design Kits’ (‘PDKs’) unless they include libraries implementing functions or technologies for items specified in 3A001 or 3A501.
Technical Notes:	Technical Notes:	Technical Notes:
1.	For the purposes of 3E505, a ‘process recipe’ is a set of conditions and parameters for a particular process step.	For the purposes of 3E505, a ‘process recipe’ is a set of conditions and parameters for a particular process step.
2.	For the purposes 3E505, a ‘Process Design Kit’ (‘PDK’) is a software tool provided by a semiconductor manufacturer to ensure that the required design practices and rules are taken into account in order to successfully produce a specific integrated circuit design in a specific semiconductor process, in accordance with technological and manufacturing constraints (each semiconductor manufacturing process has its particular ‘PDK’).	For the purposes 3E505, a ‘Process Design Kit’ (‘PDK’) is a software tool provided by a semiconductor manufacturer to ensure that the required design practices and rules are taken into account in order to successfully produce a specific integrated circuit design in a specific semiconductor process, in accordance with technological and manufacturing constraints (each semiconductor manufacturing process has its particular ‘PDK’).

Amendments to Category 4 - Computers

10

(1) The section headed Category 4 - Computers is amended as follows.

(2) In the section headed 4A Systems, Equipment and Components, after entry 4A102, insert—

(3) In the section headed 4D Software—

(a) in entry 4D001.a., for “4A001 to 4A004, or 4D” substitute “4A001 to 4A005, 4A507 or 4D”;

(b) at the end of entry 4D001.b.2., insert—

3.	Items specified in 4A506.b. or 4A506.c.

(4) In the section headed 4E Technology—

(a) in entry 4E001.a., for “4A” substitute “4A001, 4A003, 4A004, 4A005, 4A101, 4A102, 4A507”;

(b) at the end of entry 4E001.b.2., insert—

3.	Items specified in 4A506.b. or 4A506.c.

Amendments to Category 6 - Sensors and Lasers

11

In the section headed 6A Systems, Equipment and Components, in the Technical Note to Note 3.b.1. to entry 6A003.b.4., after “‘Instantaneous Field of View (IFOV)”, insert “’”.

12

In the section headed 7A Systems, Equipment and Components, in entry 7A105.a., for “unmanned aerial vehicles” substitute ““Unmanned Aerial Vehicles” (“UAVs”) capable of a range of 300 km,”.

Amendments to Category 9 - Aerospace and Propulsion

13

In the section headed 9A Systems, Equipment and Components—

(a) omit the Technical Note to entry 9A008.a.;

(b) in entry 9A112, for “aerial vehicles”, in each place those words occur, substitute “Aerial Vehicles”;

(c) in entry 9A115.a., for “unmanned aerial vehicle”, in both places those words occur, substitute ““Unmanned Aerial Vehicle” (“UAV”)”;

(d) in entry 9A118, for “unmanned aerial vehicles” substitute ““Unmanned Aerial Vehicles (“UAVs”) capable of a range of 300 km”;

(e) in entry 9A119, for “unmanned aerial vehicles” substitute ““Unmanned Aerial Vehicles (“UAVs”)”;

(f) in entry 9A350, for “unmanned aerial vehicles”, in both places those words occur, substitute ““Unmanned Aerial Vehicles (“UAVs”)”.

Part 4 — AMENDMENTS TO REGULATION (EU) 2019/125

Amendments to Regulation (EU) 2019/125

14

Regulation (EU) 2019/125 of the European Parliament and of the Council of 16 January 2019 concerning trade in certain goods which could be used for capital punishment, torture or other cruel, inhuman or degrading treatment or punishment (codification) is amended in accordance with regulations 15 to 17.

Amendment to Article 2 (Definitions)

15

In Article 2 (Definitions), at the end, insert the following definition—

“ordinary handcuffs” means handcuffs which meet all the following conditions: their overall dimension including chain, measured from the outer edge of one cuff to the outer edge of the other cuff, is between 150 and 280 mm when both cuffs are locked; the inside circumference of each cuff is a maximum of 165 mm when the ratchet is engaged at the last notch entering the locking mechanism; the inside circumference of each cuff is a minimum of 200 mm when the ratchet is engaged at the first notch entering the locking mechanism; and the cuffs have not been modified to cause physical pain or suffering.

Amendments to Annex II (list of goods referred to in Articles 3 and 4)

16

In Annex II (list of goods referred to in Articles 3 and 4), after the Introductory Note, Notes and the NB, for the table substitute—

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4A506	Quantum computers and related “electronic assemblies” and components therefor, as follows:	Quantum computers and related “electronic assemblies” and components therefor, as follows:	Quantum computers and related “electronic assemblies” and components therefor, as follows:
	a.	Quantum computers as follows:	Quantum computers as follows:
		1.	Quantum computers supporting 34 or more, but fewer than 100, ‘fully controlled’, ‘connected’ and ‘working’ ‘physical qubits’, and having a 'C-NOT error' of less than or equal to 10 ⁻⁴;
		2.	Quantum computers supporting 100 or more, but fewer than 200, ‘fully controlled’, ‘connected’ and ‘working’ ‘physical qubits’, and having a ‘C-NOT error’ of less than or equal to 10 ⁻³;
		3.	Quantum computers supporting 200 or more, but fewer than 350, ‘fully controlled’, ‘connected’ and ‘working’ ‘physical qubits’, and having a ‘C-NOT error’ of less than or equal to 2 x10 ⁻³;
		4.	Quantum computers supporting 350 or more, but fewer than 500, ‘fully controlled’, ‘connected’ and ‘working’ ‘physical qubits’, and having a ‘C-NOT error’ of less than or equal to 3 x10 ⁻³;
		5.	Quantum computers supporting 500 or more, but fewer than 700, ‘fully controlled’, ‘connected’ and ‘working’ ‘physical’, and having a ‘C-NOT error’ of less than or equal to 4 x 10 ⁻³;
		6.	Quantum computers supporting 700 or more, but fewer than 1 100, ‘fully controlled’, ‘connected’ and ‘working’ ‘physical qubits’, and having a ‘C-NOT error’ of less than or equal to 5 x 10 ⁻³;
		7.	Quantum computers supporting 1 100 or more, but fewer than 2 000, ‘fully controlled’, ‘connected’ and ‘working’ ‘physical qubits’, and having a ‘C-NOT error’ of less than or equal to 6 x 10 ⁻³;
		8.	Quantum computers supporting 2 000 or more ‘fully controlled’, ‘connected’ and ‘working’ ‘physical qubits’;
	b.	Qubit devices and qubit circuits, containing or supporting arrays of ‘physical qubits’, and specially designed for items specified in 4A506.a.;	Qubit devices and qubit circuits, containing or supporting arrays of ‘physical qubits’, and specially designed for items specified in 4A506.a.;
	c.	Quantum control components and quantum measurement devices, specially designed for items specified in 4A506.a.;	Quantum control components and quantum measurement devices, specially designed for items specified in 4A506.a.;
Note 1.: 4A506 controls circuit model (or gate-based) and one-way (or measurement-based) quantum computers. This entry does not apply to adiabatic (or annealing) quantum computers.	Note 1.: 4A506 controls circuit model (or gate-based) and one-way (or measurement-based) quantum computers. This entry does not apply to adiabatic (or annealing) quantum computers.	Note 1.: 4A506 controls circuit model (or gate-based) and one-way (or measurement-based) quantum computers. This entry does not apply to adiabatic (or annealing) quantum computers.	Note 1.: 4A506 controls circuit model (or gate-based) and one-way (or measurement-based) quantum computers. This entry does not apply to adiabatic (or annealing) quantum computers.
Note 2.: Items specified in 4A506 may not necessarily physically contain any qubits. For example, quantum computers based on photonic schemes do not permanently contain a physical item that can be identified as a qubit. Instead, the photonic qubits are generated while the computer is operating and then later discarded.	Note 2.: Items specified in 4A506 may not necessarily physically contain any qubits. For example, quantum computers based on photonic schemes do not permanently contain a physical item that can be identified as a qubit. Instead, the photonic qubits are generated while the computer is operating and then later discarded.	Note 2.: Items specified in 4A506 may not necessarily physically contain any qubits. For example, quantum computers based on photonic schemes do not permanently contain a physical item that can be identified as a qubit. Instead, the photonic qubits are generated while the computer is operating and then later discarded.	Note 2.: Items specified in 4A506 may not necessarily physically contain any qubits. For example, quantum computers based on photonic schemes do not permanently contain a physical item that can be identified as a qubit. Instead, the photonic qubits are generated while the computer is operating and then later discarded.
Note 3.: Items specified in 4A506.b. include semiconductor, superconducting, and photonic qubit chips and chip arrays; surface ion trap arrays; other qubit confinement technologies; and coherent interconnects between such items.	Note 3.: Items specified in 4A506.b. include semiconductor, superconducting, and photonic qubit chips and chip arrays; surface ion trap arrays; other qubit confinement technologies; and coherent interconnects between such items.	Note 3.: Items specified in 4A506.b. include semiconductor, superconducting, and photonic qubit chips and chip arrays; surface ion trap arrays; other qubit confinement technologies; and coherent interconnects between such items.	Note 3.: Items specified in 4A506.b. include semiconductor, superconducting, and photonic qubit chips and chip arrays; surface ion trap arrays; other qubit confinement technologies; and coherent interconnects between such items.
Note 4.: 4A506.c. controls items designed for calibrating, initialising, manipulating or measuring the resident qubits of a quantum computer.	Note 4.: 4A506.c. controls items designed for calibrating, initialising, manipulating or measuring the resident qubits of a quantum computer.	Note 4.: 4A506.c. controls items designed for calibrating, initialising, manipulating or measuring the resident qubits of a quantum computer.	Note 4.: 4A506.c. controls items designed for calibrating, initialising, manipulating or measuring the resident qubits of a quantum computer.
Technical Notes: For the purposes of 4A506:	Technical Notes: For the purposes of 4A506:	Technical Notes: For the purposes of 4A506:	Technical Notes: For the purposes of 4A506:
1.	A ‘physical qubit’ is a two-level quantum system used to represent the elementary unit of quantum logic by means of manipulations and measurements that are not error corrected. ‘Physical qubits’ are distinguished from logical qubits, in that logical qubits are error corrected qubits comprised of many ‘physical qubits’.	A ‘physical qubit’ is a two-level quantum system used to represent the elementary unit of quantum logic by means of manipulations and measurements that are not error corrected. ‘Physical qubits’ are distinguished from logical qubits, in that logical qubits are error corrected qubits comprised of many ‘physical qubits’.	A ‘physical qubit’ is a two-level quantum system used to represent the elementary unit of quantum logic by means of manipulations and measurements that are not error corrected. ‘Physical qubits’ are distinguished from logical qubits, in that logical qubits are error corrected qubits comprised of many ‘physical qubits’.
2.	‘Fully controlled’ means the ‘physical qubit’ can be calibrated, initialised, gated, and read out, as necessary.	‘Fully controlled’ means the ‘physical qubit’ can be calibrated, initialised, gated, and read out, as necessary.	‘Fully controlled’ means the ‘physical qubit’ can be calibrated, initialised, gated, and read out, as necessary.
3.	‘Connected’ means that two-qubit gate operations can be performed between any arbitrary pair of the available ‘working’ ‘physical qubits’. This does not necessarily entail all-to-all connectivity.	‘Connected’ means that two-qubit gate operations can be performed between any arbitrary pair of the available ‘working’ ‘physical qubits’. This does not necessarily entail all-to-all connectivity.	‘Connected’ means that two-qubit gate operations can be performed between any arbitrary pair of the available ‘working’ ‘physical qubits’. This does not necessarily entail all-to-all connectivity.
4.	‘Working’ means that the ‘physical qubit’ performs universal quantum computational work according to the system specifications for qubit operational fidelity.	‘Working’ means that the ‘physical qubit’ performs universal quantum computational work according to the system specifications for qubit operational fidelity.	‘Working’ means that the ‘physical qubit’ performs universal quantum computational work according to the system specifications for qubit operational fidelity.
5.	Supporting 34 or more ‘fully controlled’, ‘connected’, ‘working’ ‘physical qubits’ refers to the capability of a quantum computer to confine, control, measure and process the quantum information embodied in 34 or more ‘physical qubits’.	Supporting 34 or more ‘fully controlled’, ‘connected’, ‘working’ ‘physical qubits’ refers to the capability of a quantum computer to confine, control, measure and process the quantum information embodied in 34 or more ‘physical qubits’.	Supporting 34 or more ‘fully controlled’, ‘connected’, ‘working’ ‘physical qubits’ refers to the capability of a quantum computer to confine, control, measure and process the quantum information embodied in 34 or more ‘physical qubits’.
6.	‘C-NOT error’ is the average physical gate error for the nearest neighbour two-’physical qubit’ Controlled-NOT (C-NOT) gates.	‘C-NOT error’ is the average physical gate error for the nearest neighbour two-’physical qubit’ Controlled-NOT (C-NOT) gates.	‘C-NOT error’ is the average physical gate error for the nearest neighbour two-’physical qubit’ Controlled-NOT (C-NOT) gates.
4A507	Computers, “electronic assemblies” and components containing one or more integrated circuits specified in 3A501.a.16.	Computers, “electronic assemblies” and components containing one or more integrated circuits specified in 3A501.a.16.	Computers, “electronic assemblies” and components containing one or more integrated circuits specified in 3A501.a.16.
Note: 4A507 includes “digital computers” and hybrid computers.	Note: 4A507 includes “digital computers” and hybrid computers.	Note: 4A507 includes “digital computers” and hybrid computers.	Note: 4A507 includes “digital computers” and hybrid computers.